1. Field of the Invention
This invention relates to the design of integrated circuit memory arrays, and more specifically relates to reading data stored within a memory array.
2. Description of Related Art
An array configuration is a highly useful and frequently encountered structure for storing data within an integrated circuit. In many common arrangements, a two-dimensional array of storage elements (also known as memory cells) is arranged into rows and columns, with each memory cell connected to an associated row and column. A group of memory cells is selected by activating a row line (also known as a wordline) to which all the cells of the group are connected. This enables each of the memory cells within the group, when in a read mode, to drive its associated column line (also known as a bitline) in a manner corresponding to the data stored within each memory cell. Alternatively, when in the write mode, each memory cell is enabled to receive data conveyed on the bitline to the memory cell.
There are many ways to arrange a bitline configuration and an associated read circuit. One well known technique uses a cross-coupled sense amplifier, or "sense amp". Typically a pair of bitlines couple each of the two sides of a cross-coupled memory cell to a differential amplifier which resolves a slight difference in voltage between the two bitlines into a stable, full-level value (which may then be further decoded and eventually routed to an output signal). Sense amp circuits are constructed from a hi-stable circuit block (such as a cross-coupled differential pair of transistors) which is forced into an unstable state just before the bitlines are to be sensed. During sensing, a slight differential input from the bitlines pushes the sense amp into one of two stable states (corresponding to reading a logic "1" or a logic "0"). Consequently, sense amp circuits consume significant power while actually sensing the bitlines.
Alternatively, a separate line, known as a "write line", may be employed for writing a selected memory cell within a column of memory cells, and a separate line, known as a "read line", may be used for reading a selected memory cell within the column of memory cells. Such write and read lines may be configured as differential lines (and which therefore each employ two wires). To save area another well known technique uses a single read line to sense data within a memory cell, and is frequently known as a "single-ended" read (as opposed to a differential read as in the differential sense amp discussed above). While several variations are possible, one frequently encountered configuration precharges each read line high. When a memory cell is enabled by a read select line, the read line is either discharged by the memory cell (such as for a logic "0") or the read line is left in the precharged state (such as for a logic "1").
Such a single-ended read structure typically requires a greater voltage transition on the read line for proper sensing to occur than for a differential sense amp configuration. However, the single-ended read line configuration is more efficient for multi-port RAMs because each read port requires a separate read line for each column of memory cells within the array. The finite number of available metal lines through a memory array either limits the number of read ports which may be implemented, or requires usage of a larger memory cell layout just to support the additional read lines necessary for each read port. Since a single-ended read configuration requires only one metal line per read line for each column of memory cells in the array, such a configuration allows twice as many read ports as would a differential sense amp configuration, which requires two metal lines for each "read line" equivalent.
FIG. 1 illustrates the interconnections necessary for a multi-port memory cell 10 having two write ports and four read ports (a "2W-4R" memory cell). The read ports are single-ended read ports as described above, and consequently have one metal wire for each read line. A read select line for a given port directs the memory cell 10 to drive a corresponding read line for each port. Thus, read select lines RDSEL1, RDSEL2, RDSEL3, and RDSEL4 and read lines RDBIT1, RDB1T2, RDBIT3, and RDBIT4 allow for independent reading of the logic level stored within the memory cell 10 by each of the four read ports. Also shown in FIG. 1 are two write select lines, WRSEL1 and WRSEL2, for enabling the memory cell 10 to respond to data conveyed to the cell on either of two write data lines WRBIT1 and WRB1T2, respectively. For convenience, the group of four read lines RDBIT1-RDBIT4 may also be referred to as a read bus RDBITx. Similarly, the group of four read select lines RDSEL1-RDSEL4 may be referred to as read select bus RDSELx, the group of two write select lines WRSEL1-WRSEL2 may be referred to as write select bus WRSELx, and the group of two write data lines WRBIT1-WRBIT2 may be referred to as write data bus WRBITx.
Referring now to FIG. 2, an array 20 illustrates a traditional array configuration using a group of memory cells such as that shown in FIG. 1. For simplicity of discussion a 3.times.3 array is shown, but one skilled in the art will immediately recognize the extendibility of such an array. A decoder 22 generates each of the four signals within read select bus RDSELx1, which bus is connected to each of memory cells MC11, MC12, and MC13 within the first row of memory cells of array 20. Similarly, the decoder 22 generates each of the two signals within write select bus WRSELx1, which bus is also connected to each of the same three memory cells MC11, MC12, and MC13. Read select busses RDSELx2 and RDSELx3 service the second row (MC21, MC22, and MC23) and third row (MC31, MC32, and MC33) of memory cells, respectively, as do write select busses WRSELx2 and WRSELx3, respectively.
In the column direction, write data bus WRBITx1 is connected to each of the memory cells MC11, MC21, and MC31 within the first column of the array 20. Likewise, write data busses WRBITx2 and WRBITx3 are connected to the second column (MC12, MC22, and MC32) and third column (MC13, MC23, and MC33) of memory cells, respectively. Similarly, read line busses RDBITx1, RDBITx2, and RDBITx3 are connected to the first column, the second column, and the third column of memory cells, respectively. The write data busses and the read line busses are typically, although not always, connected to an I/O block which includes various buffers and decoders, which for clarity is not shown in FIG. 2.
As can be seen in the array 20 of FIG. 2, each memory cell is connected to a read line for each of four read ports. Within a given column of the array 20, a given read line is connected to every memory cell within the column. Since the speed of the read line is constrained by the capacitive loading upon the read line, a longer read line is more difficult to sense quickly. One constraint on the speed of a read line is the capacitive loading placed upon a read line by each memory cell. This capacitive loading arises from the read line traversing above other conductive structures within the memory cell, as well as from junction capacitance and gate overlap capacitance within each of the memory cells. This capacitive loading increases as additional memory cells are connected to each read line, which tends to slow the discharge of the read line when reading a logic "0". Since a great proportion of the capacitive loading placed upon a read line by a memory cell arises from the junction capacitance of the drain diffusion of a transistor within the memory cell used to discharge the read line, using a larger discharge transistor increases the available current but also increases the total capacitive load on the read line, and thus does not afford much increase in speed.